ASIC Verification Engineer - UVM from scratch

Cambridge, MA 02139

Posted: 09/13/2023 Employment Type: Contract Industry: Corporate Job Number: 241275

Job Description

Title: ASIC Verification Engineer – UVM

Location: Cambridge MA (remote is available)

Duration: 12 months with likely extensions

Clearance: Active preferred, will process for secret clearance if needed

Main requirement:

  • Ability to create a UVM testbench from scratch.


  • Draper's Digital Design Team is seeking a motivated and experienced Senior Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation, and communications.

  • You will develop verification approaches, author and execute verification plans, and use formal analysis tools. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.

Required Qualifications:

  • Ability to create a UVM testbench from scratch

  • Fluent in SystemVerilog including SVA

  • Recent experience with UVM

  • Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS)

  • Firm grasp of constrained-random and coverage-driven verification

  • Experience with formal analysis

  • Practice using Python, Perl, Bash or other scripting languages

  • Ability to work in a Linux environment

  • Strong analysis and problem-solving skills

Preferred Qualifications:

  • Experience leading verification teams

  • Experience with analog or mixed-signal simulations (AMS)

Security Requirement:

  • At a minimum, the ability to obtain a US secret clearance is required which requires proof of US citizenship.

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